The signal issue is becoming a manufacturing issue. PCIe 7.0 is essentially a PCB capability competition
In the past, when we talked about high-speed interconnection, we were always used to focusing on chips.
But after reading this report on PCIe 7.0, I have a stronger feeling: the problem lies not in the chip, but in the PCB.
When the speed enters the PAM4 era, signals are no longer just "faster", but become "more fragile"; when the fault-tolerant space is compressed to the limit, any bit of reflection or crosstalk will be infinitely amplified.
As a result, a long-neglected aspect has come to the forefront - PCB, which is no longer just a carrier, but is becoming a performance bottleneck.
In this article, I aim to clarify what changes have taken place in PCBs in the era of PCIe 7.0.

 

 

1. What does this material really want to illustrate?
With PCIe 7.0 entering the PAM4 era, the bottleneck has shifted from chips to PCBs - high-speed interconnects are evolving from being a "circuit issue" to a "manufacturing precision issue".

 

 

II. Essential changes in PCIe 7.0: from NRZ to PAM4, with a sharp decrease in fault tolerance
Data rate continues to double (PCIe generational evolution)
The signal is converted from NRZ to PAM4
Key changes:
PAM4 has higher requirements for signal-to-noise ratio
The margin for error has significantly narrowed
Conclusion: It's not that the signal is faster, but rather that it is "more fragile"

 

 

 

III. Core issue shifts: reflection + crosstalk become the primary contradiction
In typical topology:
Via (via hole)
Breakout (fan-out)
Wiring density
Become the main source of problems
The document is clear:
Reflection & crosstalk control = key to achieving PCIe 7.0
Conclusion: The core of high-speed interconnection has shifted from "transmission" to "interference control"

 

 

 

IV. Essential breakthrough of PCB: comprehensive size reduction (extreme miniaturization)
From the comparison of processes, we can see that:

 

 

Core trends:
A shorter stub
Smaller via
Thinner thread
Conclusion: PCB is entering the era of micro-shrinking of "quasi-advanced processes"

 

 

V. Three major technological breakthroughs
🔷 ① Backdrilling upgrade with Stub can achieve 1±1mil
The depth control is more precise, resulting in smaller errors
Function: Reduce reflection (the most critical variable)
🔷 ② High-precision registration with multiple Mark points + AI recognition
Enhanced resistance to plate deformation
Essence: moving from "mechanical precision" to the integration of "algorithms + manufacturing"
🔷 ③ High-density fine-line etching with vacuum etching + LDI exposure
Reduce lateral erosion and improve line width accuracy
Essence: The evolution of PCB manufacturing capability towards "semiconductor process integration"

 

 

VI. Design verification conclusion: All optimizations point in the same direction
The experimental data is crystal clear:
Trend summary:
The shorter the stub, the lower the loss
The smaller the Via, the lower the crosstalk by 4~5dB
The thinner the trace, the lower the crosstalk by 3~4dB
Air filling is superior to resin filling
Core conclusion: All optimizations, in essence, aim to "reduce parasitic structures"

 

 

 

 

Editor's summary
PCIe 7.0 is not a mere speed upgrade, but a comprehensive approach to the limits of PCB manufacturing: as PAM4 significantly reduces signal fault tolerance, reflection and crosstalk become the dominant issues, transforming the PCB from a "supporting platform" into a "performance bottleneck".
The essence of competition in high-speed interconnection in the future lies not in chips, but in who can make PCBs more refined.