Regarding the 78-layer orthogonal backplane adopted by NVIDIA's next-generation computing platform Rubin, the market has recently undergone a process from panic to reassessment. A rumor about "single-digit yield and one-year delivery delay" once triggered supply chain anxiety, but subsequent information from multiple sources showed that the real industrial landscape was not "stuck", but rather a deep adjustment centered around system architecture and advanced manufacturing processes.

  Rumor and clarification: it's not a delay, it's a change of direction
  In mid-July, Huang Renxun made it clear at the Morgan Stanley conference that the Kyber rack was being replaced by a "better solution". He emphasized that this was not a delay, but a replacement.
  NVIDIA's official roadmap remains unchanged: Rubin Ultra is still targeted for shipment in 2027, and the standard version NVL72 Rubin cabinet is scheduled for delivery in the fourth quarter of 2026. Supporting technologies such as 800V high-voltage power supply and optical interconnection between cabinets are also progressing normally according to the schedule.
  The OEM, Foxconn, provided a more moderate assessment, stating that even if there are phased adjustments to the Kyber solution, it will not affect the overall pace of chip iteration. After communication, several investment banks also agreed that the excessive concerns surrounding manufacturing delays are unfounded.
  The source of the previous fluctuations was the extremely demanding manufacturing process for the 78-layer orthogonal backplane. This backplane requires the use of M9-grade ultra-low loss copper-clad laminate, mixed with PTFE and quartz cloth, with a line width refined to the level of 25 microns.
  In the initial stage, the yield rate was indeed in the single-digit range, and major suppliers such as Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan Technology Manufacturing Company (TTM), Shin Xing, and Shenzhen Nanshan Circuit Technology Co., Ltd. were all struggling in the deep waters of yield rate improvement. The copper paste via filling process is prone to generating bubbles due to the excessive aspect ratio, which directly threatens electrical reliability and becomes another substantial engineering hurdle.
  However, Nvidia has denied the statement of "postponing for 12 months to 2028". The more accurate description of "Rubin Ultra quad-chip version being cut" should be SKU streamlining, shifting to a dual-chip version combined with Oberon Rubin to compensate, rather than project cancellation. Difficulties are real, but the narrative of "being stuck" has been significantly amplified.
  Process deep water area: three major yield killers
  For engineers involved in the manufacturing process, the mass production of 78-layer M9 backplanes is undoubtedly an extreme challenge. The current yield bottlenecks reported by the industry mainly arise from three directions:
  Moving to the manufacturing side, the mass production challenges of the 78-layer M9 backplane mainly focus on three directions. The first is lamination delamination and board cracking. The moisture absorption of M9 resin far exceeds that of traditional FR-4. Once water is absorbed, the expansion of water vapor during high-temperature lamination can cause delamination. At the same time, if the thick copper layer and sparse signal layer are arranged asymmetrically, the resin flow will be uneven, which is extremely easy to form stress concentration points.
  Next, there is the precise control of impedance under 224Gbps high-speed signals. Fluctuations in copper residue rate cause the thickness of the dielectric to vary, and the dielectric constant of different material batches is discrete. The superposition of line width tolerances can lead to significant impedance drift, directly resulting in signal eye closure. Once the differential line crosses the reference plane division, the return path is disrupted, and signal quality will further deteriorate.
  Next, we have the strict red line for high-frequency dielectric loss. At 16GHz, every 0.0005 increase in the dielectric loss factor will significantly shorten the effective transmission distance. Excessive loss often arises from damp prepreg, improper surface roughness of copper foil, or uneven thickness of electroplated copper.
  Facing these pain points, the frontline engineering team has gradually accumulated a set of stringent ironclad rules for mass production. The base material needs to be vacuum-packed and strictly controlled in temperature and humidity, and must be used within a limited time after unpacking. The lamination must be symmetrical in the center, and filled with dummy copper to balance the residual copper rate. For lamination, the M9-specific multi-stage vacuum slow-rise curve is used, which fully exhausts the air before increasing the pressure for curing.
  In terms of impedance control, it is necessary to perform simulation-based back-propagation compensation based on the measured dielectric constant and copper residue rate of each batch of materials, coupled with micrometer-level etching control and continuous stratigraphic reference. For loss control, red lines are drawn from material selection, with signal layers locked to low-roughness copper foil and quartz fiberglass cloth. The production environment is maintained at a constant temperature, surface treatment is mandatory for immersion gold, and back drilling is mandatory for vias.
  Each batch also needs to undergo multi-stage reliability screening through processes such as water boiling and soldering, with all process parameters digitally archived to ensure rapid traceability of any anomalies.